Integrated circuits are typically formed on semiconductor chips. The integrated circuits on a semiconductor chip are powered by a power supply for providing an operation voltage, often referred to as voltage-drain-drain (VDD). Therefore, the voltages in the integrated circuits are typically in the range of between a ground voltage of 0V and the operation voltage VDD.
In order to improve the reliability and performance of integrated circuits, voltages outside the typical voltage range, either higher than operation voltage VDD, or lower than ground voltage of 0V, may be needed. Exemplary circuits having such a requirement include static random access memory (SRAM) cells operated under dynamic powers. By applying voltages lower than 0V or higher than operation voltage VDD on SRAM cells, the read and write margins of the SRAM cells can be improved.
FIG. 1 illustrates a conventional bootstrap voltage generating circuit, which includes a p-type metal-oxide-semiconductor (PMOS) transistor 2 serially coupled to an n-type metal-oxide-semiconductor (NMOS) transistor 4. PMOS transistor 2 and NMOS transistor 4 are coupled between the ground and operational voltage VDD, and form an inverter, so that voltage V8 at node 8 has an inversed phase compared with voltage V6 at node 6. Capacitor 10 is coupled in series with load capacitor 12, which may be an equivalent capacitor of a load circuit.
The voltage at node 6 is a clock signal switching between 0V and operation VDD. When voltage V6 rises from 0V to VDD, voltage V8 falls from VDD to 0V. Accordingly, voltage V14 at node 14 falls from an initial voltage V1 to a lower voltage V2. If V1 is set to 0V, V2 will be lower than 0V, and there is the relationship:V2=−VDD*C12/(C10+C12)  [Eq. 1]wherein C10 and C12 are the capacitances of capacitors 10 and 12, respectively. A bootstrap voltage lower than the ground voltage is thus generated.
The circuit shown in FIG. 1 can also be used to generate a voltage higher than VDD. When voltage V6 falls from operation voltage VDD to 0V, voltage V8 rises from 0V to operation voltage VDD. Accordingly, voltage V14 at node 14 increases from an initial voltage V3 to a higher voltage V4. If V3 is set to VDD, V4 will be higher than VDD, and there is the relationship:V4=VDD*C12/(C10+C12)+VDD  [Eq. 2]
Equations 1 and 2 indicate that the bootstrap voltages V2 and V4 are linearly related to operation voltage VDD. Such bootstrap voltages suffer limitations. For example, if the performance of the load circuits shifts with the change in temperature, it is desired that bootstrap voltages also shift with the temperature in order to cancel the shift effects of the load circuit. Such a function, however, cannot be provided by conventional bootstrap voltage generating circuits. Accordingly, more flexible bootstrap voltage generating circuits are needed.